Verilog HDL,VerilogHDL
1)VerilogHDLVerilog HDL
1.A programmable logical device is programmed byVerilogHDL to realize the conversion from series to parallel for single chip computers.本文介绍了一种固定信号格式的串并转换,利用Verilog HDL 语言对一块可编程逻辑器件进行编程,实现单片机串行口输出的串行数据到8位并行数据的转换。
英文短句/例句
1.Design and Implementation of High Speed Reusable SPI Bus with Verilog HDL;高速可复用SPI总线的设计与Verilog HDL实现
2.Design of The PMW output control based on verilog HDL;基于Verilog HDL设计的PWM输出控制
3.On How to Reach the Interface Transfers of Parallel-series and Series-parallel by the Language Performs of Verilog HDL;用Verilog HDL语言实现并串、串并接口的转换
4.Using the Verilog HDL to Design the USB IP Core;USB IP Core的Verilog HDL语言设计方法
5.The design of DDS arbitrary waveform generator based on Verilog HDL基于Verilog HDL的DDS任意波形发生器设计
6.Blocking assignment property and its application in Verilog HDLVerilog HDL阻塞属性探究及其应用
7.The Summary of Doing Synthesizable By Using Design Compiler用Verilog HDL进行可综合RTL设计概述
8.Implementation of CRC in IEEE1394 Based on Verilog HDL基于Verilog HDL的IEEE1394协议中CRC校验的实现
9.Design of I~2C Bus Analysis Based Verilog HDL基于Verilog HDL的I~2C总线分析器
10.FPGA realization of SPWM entire digital algorithm based on Verilog HDL基于Verilog HDL的SPWM全数字算法的FPGA实现
11.Design and Implementation of Reusable IP Core of SPI on Besis of Verilog HDL;基于Verilog HDL的SPI可复用IP核的设计与实现
12.Research on the Modules of Reverse Access Channel of IS-95 CDMA Based on Verilog HDL;基于Verilog HDL的IS-95 CDMA反向接入信道模块的研究
13.The Research and Development of the Network Courseware for "Verilog HDL Hardware Description Language";《Verilog HDL硬件描述语言》网络课件研究与开发
14.Design and Test of CAN Bus Controller Based on Verilog HDL基于Verilog HDL语言的CAN总线控制器设计及测试
15.Design of encoder for MVB network based on verilog HDL基于Verilog HDL的多功能车辆总线编码器设计
16.Design of Convolution Coder Described by Verilog HDL基于Verilog HDL语言描述的卷积码编码器的设计
17.Design of a RISC/DSP Microprocessor IP Core Based on Verilog-HDL基于Verilog-HDL的RISC/DSP微处理器IP核的设计
18.Study of Verilog-HDL and Application in Design of Position Sensor Controller;关于对Verilog-HDL的研究及其在位移传感控制器设计中的应用
相关短句/例句
Verilog HDL descriptionsVerilog HDL描述
3)Verilog HDLVerilog HDL语言
4)Verilog-HDL languageVerilog-HDL语言
5)Verilog-A HDLVerilog-AHDL
1.Transient effects caused by wide opera- tional range in temperature were taken into account in Verilog- A HDL and implemented in Spectre Circuit Simulator.使用Verilog-AHDL语言实现,并且用Spectre电路仿真器执行,可实现宽温度范围应用。
6)Fibrinogen[英][fai"brin?d??n][美][fa?"br?n?d??n]LDL/HDL
1.The predictive value both high of serumFibrinogen and LDL/HDL for acute coronary risk;高水平的纤维蛋白原与LDL/HDL比值对冠脉风险的联合评估价值探讨
延伸阅读
HDL分子式：CAS号：性质：又称α-脂蛋白，高密度脂蛋白。用超速离心方法可将血浆脂蛋白分成乳糜微粒，极低密度脂蛋白，低密度脂蛋白，高密度脂蛋白。其中沉淀于离心管底部的那一部分称高密度脂蛋白。由于其脂质含量相对低于其他三个类别，故又称低脂质脂蛋白。含蛋白(45％～50％)，甘油三酯(5％)，胆甾醇(20％)，磷脂(30％)。分子量2×105左右。相对密度1.063～1.2。直径约10nm。主要生理功能是转运磷脂和胆固醇。
