Verilog HDL语言,Verilog HDL
1)Verilog HDLVerilog HDL语言
英文短句/例句
1.On How to Reach the Interface Transfers of Parallel-series and Series-parallel by the Language Performs of Verilog HDL;用Verilog HDL语言实现并串、串并接口的转换
2.Using the Verilog HDL to Design the USB IP Core;USB IP Core的Verilog HDL语言设计方法
3.Design and Test of CAN Bus Controller Based on Verilog HDL基于Verilog HDL语言的CAN总线控制器设计及测试
4.Design of Convolution Coder Described by Verilog HDL基于Verilog HDL语言描述的卷积码编码器的设计
5.The Research and Development of the Network Courseware for "Verilog HDL Hardware Description Language";《Verilog HDL硬件描述语言》网络课件研究与开发
6.Design and Implementation of High Speed Reusable SPI Bus with Verilog HDL;高速可复用SPI总线的设计与Verilog HDL实现
7.Design of The PMW output control based on verilog HDL;基于Verilog HDL设计的PWM输出控制
8.Design of a RISC/DSP Microprocessor IP Core Based on Verilog-HDL基于Verilog-HDL的RISC/DSP微处理器IP核的设计
9.The design of DDS arbitrary waveform generator based on Verilog HDL基于Verilog HDL的DDS任意波形发生器设计
10.Blocking assignment property and its application in Verilog HDLVerilog HDL阻塞属性探究及其应用
11.The Summary of Doing Synthesizable By Using Design Compiler用Verilog HDL进行可综合RTL设计概述
12.Implementation of CRC in IEEE1394 Based on Verilog HDL基于Verilog HDL的IEEE1394协议中CRC校验的实现
13.Design of I~2C Bus Analysis Based Verilog HDL基于Verilog HDL的I~2C总线分析器
14.FPGA realization of SPWM entire digital algorithm based on Verilog HDL基于Verilog HDL的SPWM全数字算法的FPGA实现
15.Design and Simulation of DDS Based on Verilog HDL;基于Verilog语言的DDS设计与仿真
16.Design of an Adaptive Digital Cymometer Based on Verilog HDL;基于Verilog语言的自适应数字频率计设计
17.Design and Implementation of Reusable IP Core of SPI on Besis of Verilog HDL;基于Verilog HDL的SPI可复用IP核的设计与实现
18.Research on the Modules of Reverse Access Channel of IS-95 CDMA Based on Verilog HDL;基于Verilog HDL的IS-95 CDMA反向接入信道模块的研究
相关短句/例句
Verilog-HDL languageVerilog-HDL语言
3)VerilogHDLVerilog HDL
1.A programmable logical device is programmed byVerilogHDL to realize the conversion from series to parallel for single chip computers.本文介绍了一种固定信号格式的串并转换,利用 Verilog HDL 语言对一块可编程逻辑器件进行编程,实现单片机串行口输出的串行数据到8位并行数据的转换。
4)Verilog HDL descriptionsVerilog HDL描述
5)verilog HDLVerilog语言
1.The paper realizes the design of SDXC matrix with Verilog HDL based on a improved unit architecture.通过改进传统数字交叉连接矩阵的单元结构,详细介绍了基于Verilog语言的SDXC矩阵设计的一种新方法。
6)verilogVerilog语言
1.Moduling Component with Verilog Language;使用Verilog语言建立器件模型
2.The RTL-level description of the algorithm by Verilog language is achieved.为了使算法能够在FPGA上具体实现,文中对算法进行了改进,实现了直方图统计和均衡的并行执行,利用Verilog语言对算法进行了完全可综合的RTL级描述,在Linux系统上应用Ncverilog进行了编译仿真,并利用Synplify Pro8。
延伸阅读
BASIC语言(见程序设计语言)BASIC语言(见程序设计语言)BASIC吕AS{CBASICyLJy〔1下〕语言(BASIC)见程序设计语言。
