Verilog硬件描述语言,verilog HDL
1)verilog HDLVerilog硬件描述语言
1.This article analyzes the theory of power consumption in digital circuit, writes a power consumption model in gate level using Verilog HDL according to the theory, and applies this model into three different structured adders.对数字电路中的功耗产生机理进行了分析 ,根据此原理 ,利用Verilog硬件描述语言编写了一个门级功耗模型 ,并将他应用到 3种不同结构的加法器中 ,分别测量其功耗 ,分析了功耗大小不同的原因。
2.Then, the thesis gives design details of all the major modules of the JPEG decoder which is implemented using Verilog HDL also with the simulation waveforms and the implementing results after the JPEG decoding algorithm was studied deeply.采用了Verilog硬件描述语言对JPEG基本模式硬件解码器的各主要模块进行设计实现,并给出了功能仿真波形图及测试结果。
3.The endpoints controller is designed in Verilog HDL for USB2.采用Verilog硬件描述语言设计了用于USB2。
英文短句/例句
1.A Programmable UART Based on Verilog HDL基于Verilog硬件描述语言的可编程异步收发器
2.The Research and Development of the Network Courseware for "Verilog HDL Hardware Description Language";《Verilog HDL硬件描述语言》网络课件研究与开发
3.CHDL (Computer Hardware Description Language)计算机硬件描述语言
4.Design of Convolution Coder Described by Verilog HDL基于Verilog HDL语言描述的卷积码编码器的设计
5.nonprocedural computer hardware description language非过程计算机硬件描述语言
6.An Exploration on the Teaching Reformation of the HDL Course;“硬件描述语言”课程的教学改革探索
7.The Status Quo and Development of Several Hardware Description Languages;几种硬件描述语言HDL的现状与发展
8.To design waveform pulsing with VHDL Hardware DescriPtion Language;用VHDL硬件描述语言设计波形发生器
9.Programmable logic devices and EDA way for hardware description language;可编程逻辑器件及硬件描述语言的EDA方法
10.The application of hardware description language VHSIC in design of ASIC硬件描述语言在专用集成电路设计中的应用
11.Resource Models and Hardware Synthesis for System Level Design Language;资源模型与系统级描述语言的硬件综合
12.On the Synthetically VHDL Hardware Description Language Under the Max+PlusⅡ Software;基于Max+PlusⅡ平台对VHDL硬件描述语言综合的探讨
13.Describing basic logic openration in the digital circuit with hard description数字电路基本逻辑运算的硬件语言描述与应用
14.Construction of"Language to Describe"the Teaching of Computer Hardware Platform构建“类描述语言”的计算机硬件教学平台
15.Advanced Boolean Expression Language is a big breakthrough in the development of the electronics system.硬件描述语言是当代电子系统发展的一个重大突破。
16.Research and Implementation of Parallel Logic Simulation System Based on VHDL;基于硬件描述语言的并行逻辑模拟系统研究与实现
17.The Investigation of the Combinatory Logic Circuit Design Based on the ABEL-HDL;基于硬件描述语言ABEL-HDL实现组合逻辑电路的探讨
18.A Survey of Software Architecture Description Language ADL;软件构架描述语言ADL的研究进展
相关短句/例句
Verilog hardware description languageVerilog硬件描述语言
1.CPLD is chosen as the hardware design platform,and the driving schedule generator is described withVerilog hardware description language.选用复杂可编程逻辑器件(CPLD)作为硬件设计平台,使用Verilog硬件描述语言对该驱动时序发生器进行了硬件描述。
3)Verilog HDL硬件描述语言Verilog
4)VHDL/Veriloy/LanguageVHDL/Verilog硬件描述语言
5)VHDL硬件描述语言(VHDL)
6)HDL硬件描述语言
1.Implementation of Viterbi Decoding With VerilogHDL;用Verilog硬件描述语言实现Viterbi译码
2.Building ofHDL MP3 Decoder′s Test Bench and IP Core Reuse;基于硬件描述语言的MP3解码器仿真平台的搭建以及IP Core的重用
3.Designing Digital-Calculagraph By VerilogHDL;用Verilog硬件描述语言设计数字计时器
延伸阅读
图像描述语言用于描述图像的一种形式语言。这种语言的句子用表示基元（见模式文法）的终止符、连接算符和括号组成的链表示，它是1969年由C.肖建立的。首先在每个基元上选定两个不同的点，分别标记为头(h)和尾(t)，然后规定一个一元算符～和一组二元算符{+,-,×,*}，使基元或子模式可在头、尾处连接起来。这些算符的意义如图1。～a是将a的头尾颠倒;a+b是将b的尾与a的头连接；a-b是将b的头与a的头连接;a×b是将b的尾与a的尾连接；a*b是将b的头和尾分别与 a的头和尾连接。四种连接运算所得结果的头和尾都分别是b的头和a的尾。例如,图2上方ɑ，b，c，d表示基元，那么，其下方的图像可以由(b+(b-c)+c+d+(d×(～b))+(～b))*(a+(b+a+(～b))*a+a)描述。设VT＝｛b|b为基元｝∪{+,-,×,*,～,(,)}，则以VT为终止符集的适当的短语结构文法，能够生成图像描述语言。例如，上下文无关文法G＝({S，A，B},{ɑ，b,+,×,(,)},P，S),其中P＝{S─→B+(B+A)×(A),A─→a+A，A─→ɑ，B─→b+B，B─→b},可以用来对各种尺寸的字符进行描述。图像描述语言可以用链表示某些二维图像，所以在句法模式识别中得到较多的应用。参考书目K.S.Fu，Syntactic Pattern Recognitionand Applications，Prentice-Hall，Englewood Cliffs, N.J.,1982.
